CMOS, single-ended to differential conversion circuits which allow a signal referenced to a ground potential to be converted to a fully balanced differential signal are currently available for use in data processing systems. Generally, by converting a single-ended signal to a differential signal, the dynamic range and quality of the signal may be more easily preserved. Furthermore, differential signals are typically less sensitive to power supply noise and are capable of achieving a dynamic range which is approximately twice that of a single-ended signal. Another advantage of implementing such CMOS single-ended to differential conversion circuits is that a signal may be sampled and held during the conversion operation.
There are few prior art circuits which convert a single-ended signal to a differential signal without introducing errors. Therefore, several causes of error must be overcome to preserve signal quality. To preserve signal quality, the circuit must have good power supply rejection to be operated on a same silicon substrate as other circuits which produce noise. Power supply rejection refers to the ability of a circuit to reject or attenuate any noise which is introduced onto the power supply. Digital circuits are examples of such noise producing circuits. Also, the circuit which preserves signal quality must be capable of compensating for a difference between a d.c. component of the single-ended signal and the common mode of the differential output signal such that no distortion components are introduced in the differential output signal. It should be noted herein that the common mode of a differential signal is the average value of the two components of the signal. Additionally, the circuit must be capable of removing offset voltages and low frequency noise from any active amplifiers which are used in a conversion process.
A prior art circuit is disclosed in U.S. Pat. No. 4,647,865 by Alan L. Westwick and assigned to Motorola, Inc. In U.S. Pat. No. 4,647,865, a single-ended signal is converted to a differential signal through the use of switches, capacitors and a operational amplifier. On one clock phase, the single-ended input signal is sampled on two series-connected capacitors. On the second clock phase, the charges on these two capacitors are transferred to a pair of integrating capacitors. The pair of integrating capacitors are connected in negative feedback around the operational amplifier. The circuit disclosed in U.S. Pat. No. 4,647,865 converts an input signal to a fully balanced differential signal with all of the attributes mentioned above. However, if the operational amplifier contains an input referred offset voltage or low frequency noise, then the offset voltage and the low frequency noise are summed with the differential signal. This addition of a constant or low frequency signal quantity to the signal being processed is undesirable in many applications.